An increasingly common nonvolatile semiconductor memory is referred to as a "flash" memory. A flash memory includes an array of electrically programmable and electrically erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor, including a floating gate between a control (input) gate and a channel. Information is stored in the memory cells by storing a charge on the floating gate which adjusts a Vt (threshold voltage) of the transistor. The threshold voltage is the voltage that must be overcome by the gate to source voltage (Vgs) to activate the device.
For example, Vt for a typical transistor with no charge stored on its floating gate is approximately six volts. This means that a voltage of at least six volts must be applied between the control gate and the source junction for the device to activate, that is, to allow current to flow through the device. If a charge is present on the floating gate Vt is effectively raised by the charge present. The net effect of this is that an intermediate voltage (a sense voltage) can be applied between the source and the control gate and if the transistor activates it is not programmed and if the transistor does not activate it is programmed.
The memory cells in the array are accessed via a plurality of column lines (digit lines) and a plurality of row lines (word lines). Each of the column lines is coupled to the drain of a corresponding memory cell transistor, and each of the row lines is coupled to a control gate of a corresponding memory cell transistor. The respective column and row lines are driven by address decoder and timing circuitry.
In the manufacture of flash memory arrays, it is not uncommon for one or more memory cells in a row of the array to become defective. Such defects are commonly caused by a short between a column line and a row line associated with a particular memory cell. In other words, the drain and control gate of the transistors within a particular defective row are shorted together. Other types of defects can also occur, such as single bit or multiple bit failures.
In memory devices other than flash memory arrays, specifically dynamic random-access memories (DRAMs), one solution to this problem is to replace a particular defective row and/or column by addressing a redundant row and/or column. This is not a solution for flash memory arrays, however. Unlike DRAM arrays, all sources in a particular sector of flash cells are tied together to allow for erasing of all transistors simultaneously. It becomes apparent that tying together all the sources in a sector within a flash memory array precludes using the redundancy approach when considering the operation of a flash memory device. In a typical flash device, a programmed transistor has a Vt of six volts and an unprogrammed transistor Vt is zero volts. An unprogrammed cell (one which conducts at the sense voltage) can be arbitrarily assigned a logic 1 value, while a programmed cell (one which does not conduct at the sense voltage) can be assigned a logic 0 value. To reprogram a flash memory device, all the transistors are preprogrammed to six volts and then erased to zero volts. Next, a charge is stored on the floating gate of only on those transistors to be programmed. If the transistors are not first preprogrammed but only erased, those already having no charge on the floating gate fall into depletion mode since they would be erased to a negative Vt.
However, if a redundant row is used within a flash device the replaced row is not preprogrammed because the preprogramming is directed to the redundant row. The replaced row would be erased however because the sources of the transistors within the defective row are common to the sources of all the transistors within a particular sector, and all transistors in the sector, including the replaced row, will be erased. With each reprogramming of the flash memory, the replaced row falls deeper and deeper into depletion mode since it is bypassed during programming. Any depletion mode transistors within a sector affects the performance of other transistors within that sector as is known in the art. Therefore, the approach commonly employed by DRAMs cannot be used by flash memories.
There is, therefore, a need for an improved flash memory and an associated control circuit to overcome the above-mentioned deficiencies.